This invention relates to multi-layer capacitor structures, and to methods for forming the same.
As the complexity of integrated circuits increases, logic devices are switched at ever increasing rates to increase device performance. However, digital integrated circuits require both stable voltage references and uniform power distribution among all integrated logic devices for signal definition. Higher switching rates result in increased amounts of associated electrical switching noise, which can substantially affect the stability and the uniformity of the operational voltages associated with each logic device.
It is well known that switching noise of a circuit stage can be reduced by minimizing the inductance as well as maximizing the capacitance, of the electrical path that exists between the power and ground terminals. Capacitors are generally used to reduce power supply and ground supply noise and to improve the switching speed by providing necessary transient currents during a switching event. When these capacitors discharge their current into the device, they quickly recharge from energy stored in slower discharging capacitors and power supplies. However, current capacitive methods and structures for reducing noise on an integrated circuit are not always adequate, especially at higher frequencies of operation.
For example, one known technique for reducing switching noise is to utilize a decoupling capacitor between associated voltage pins. However, since a discrete capacitor is necessarily mounted a certain distance away from the semiconductor chip, it is electrically coupled to the voltage pins by a plurality of power wiring lines or large power buses which typically represent high induction paths which add to the effective inductance of the electrical path. Further, as the amount of current flowing in the plurality of wiring lines increases, a voltage drop is produced across the wires which adds additional power distribution noise. Also, in such a configuration, a significant amount of resistance exists between the capacitor and the switching logic which reduces the amount of transient current the capacitor can provide, which limits its noise suppression capability, and which slows down the speed of the switching circuits.
One technique of minimizing the effective inductance of the electrical paths is to move the decoupling capacitor as close to the semiconductor chip as possible. However, in view of either the layout of the wiring lines associated with the semiconductor chip and/or the physical dimensions of the discrete capacitor itself, it is not possible to physically position the discrete capacitor so that there is no voltage drop or switching noise. Further, externally mounted decoupling capacitors occupy considerable surface area, increase the overall cost of a completed integrated circuit unit, and the assembly of a number of individual capacitors can be cumbersome and prone to error.
An alternative capacitive structure which is used to reduce switching noise is discussed in U.S. Pat. No. 4,916,576 to Herbert. This patent describes a multipin matrix capacitor having a plurality of distributed terminals along each electrode to provide shorter conduction path lengths between an external component and the capacitor to reduce capacitive lead inductances. However, the conduction path lengths between the external component and the capacitor are limited by the fact that connections to the capacitor structure can only be made around the outside edges of the capacitive element. Further, since the capacitor is not manufactured integral with the external component, it is isolated by the board and package inductance, which severely reduces its effectiveness in reducing switching noise.
Another method of providing decoupling capacitance within an integrated circuit is described in U.S. Pat. No. 5,789,807 to Correale, Jr. This patent discloses a power conductor structure which staggers power and ground conductors such that a first power connector in one outer plane is connected to a second power conductor in the other outer plane that is displaced vertically and laterally from the first power conductor. The resulting structure improves power supply decoupling by providing increased capacitance associated with the power distribution of the integrated circuit. However, since the individual power and ground conductors are formed as a wire grid, they do not have the capacitive character of substantially planar ground planes. Further, since the power and ground conductors also carry chip-level voltage signals, low-dielectric constant materials will be disposed between the conductors. The resulting decoupling capacitance provided across the integrated circuit is likely to be insufficient to suppress the high levels of noise which occur at high frequencies and as a result, additional decoupling capacitors may be required.
Accordingly, there is a need for an improved distributed high density capacitive structure which can be used to provide locally accessible capacitance to various switching logic gates resident on an integrated circuit, which introduces substantially low levels of inductance and resistance into the electric path, and which is easy to fabricate and customize for high frequency application.
It is therefore an object of the present invention, to provide a multi-layer distributed capacitance structure comprising:
(a) a substrate, and a bottom electrode layer overlying said substrate,
(b) at least one pair of intermediate layers of an electrode and a dielectric material overlying said bottom electrode,
(c) a top pair of layers of an electrode and a dielectric material overlying the uppermost pair of intermediate layers,
(d) a plurality of openings in said structure, each opening extending from said top pair of layers and through at least one pair of said intermediate layers, at least some of said openings penetrating all of said pairs of intermediate layers,
(e) each opening having a sidewall, at least a portion of said sidewall having an inwardly and downwardly stepped configuration in said opening so that at least some of said layers of electrodes in said openings have edge portions in said openings that are not covered by an electrode layer thereabove, and
(f) at least some of said edge portions being adapted to be connected to a circuit.
In another aspect the invention provides a method for fabricating a multi-layer film capacitor structure, comprising the steps of:
(a) providing a substrate,
(b) establishing a bottom electrode layer over said substrate,
(c) establishing at least one pair of intermediate layers of an electrode and a dielectric material over said bottom electrode,
(d) establishing a top pair of an electrode and a dielectric material over said intermediate layers, and
(e) removing portions of said electrode and dielectric material layers such that a plurality of openings are formed in said structure, each said opening extending from said top pair of layers and through at least one pair of said intermediate layers with at least some of said openings penetrating all of said pairs of intermediate layers.
In another aspect the invention provides a method of fabricating a multi-layer distributed capacitor structure, comprising the steps of.
(a) providing a substrate,
(b) establishing a bottom electrode layer over said substrate,
(c) establishing at least one pair of intermediate layers of an electrode and a dielectric material over said bottom electrode,
(d) establishing a top pair of an electrode and a dielectric material over said intermediate layers, and
(e) such that said electrode and dielectric material layers together form a structure having a plurality of openings, each said opening extending from said top pair of layers and through at least one pair of said intermediate layers with at least some of said openings penetrating all of said pairs of intermediate layers.
Further objects and advantages of the invention will appear from the following description, taken together with the accompanying drawings.